Technological Field
The present technology relates to a memory array architecture that can achieve a high read/write speed. The present technology can be applied to phase change memory (PCM) architectures, and can achieve this high read/write speed by utilizing a double-data-rate interface.
Description of Related Art
Storage class memory (SCM) has recently received increased attention due to its ability to improve performance and reduce power consumption of a computer system (Rich Freitas, et. al., “Storage Class Memory, the next storage system technology”, in IBM J. RES. & DEV. VOL. 52 NO. 4/5, pp. 439-447, 2008). Generally, SCM is divided into different memory types based on random access speed. For example, SCM is divided into memory type (M-type) and storage type (S-Type). The performance of M-type SCM is close to DRAM. In contrast, the performance of S-type SCM is closer to that of a disk drive.
NAND type flash memory and three-dimensional (3D) NAND type flash memory have been widely used, or considered for use, as S-type SCM, but NAND and 3D NAND type flash memory technologies may not be able to meet recent performance and endurance requirements of M-type SCM (e.g., DRAM). However, DRAM is a volatile memory technology, making it desirable to provide a non-volatile technology that operates within the required performance specifications of M-type SCM. In view of the above, the following have emerged as possible candidates for M-type SCM applications: (i) phase change memory (PCM); (ii) resistive random-access memory (ReRAM) incorporating transition metal oxides; and (iii) spin transfer torque magnetic RAM (STTMRAM). Among these, PCM may be the most mature and promising non-volatile memory technology for M-type SCM applications.
In PCM, each memory cell includes a phase change material. The phase change material can change between a crystalline phase and an amorphous phase. The amorphous phase is characterized by higher electrical resistivity than the crystalline phase. During operation of the PCM, an electrical current pulse passed through a memory cell of the PCM can set and reset the solid phase in an active region of the phase change material (i.e., the electrical current pulse can be used to change the PCM between the higher resistivity amorphous phase and the lower resistivity crystalline phase).
The change from the amorphous phase to the crystalline phase, referred to herein as a SET operation, may be performed by applying an electrical pulse to the phase change material. The electrical pulse can include an initial peak current that is followed by decreasing current over a duration of the electrical pulse so that the phase change material slowly cools into the crystalline phase.
The change from the crystalline phase to the amorphous phase, referred to herein as the RESET operation, may be performed by applying a short and high current electrical pulse to the phase change material to melt or break down the crystalline phase structure of the phase change material. Afterwards the phase change material cools quickly (e.g., the phase change material is quenched). This quenching of the phase change material and allows at least a portion of the phase change material to stabilize in the amorphous phase.
As previously explained, in order to achieve similar performance of working memory of, for example, a computing device, a read/write bandwidth and latency of the M-type SCM needs to be as close to DRAM as possible. However, until recently PCM has not been a good candidate for M-type SCM because the phase changes are relatively slow, and PCM typically uses a lower performance non-volatile memory interface and array architectures. For example, around the year 2012 PCM had a read speed of approximately 400 MB/s and a write speed of approximately 40 MB/s (Youngdon Choi, et. al., “A 20 nm 1.8V 8 Gb PRAM with 40 MB/s Program Bandwidth”, in ISSCC Dig. Tech. Papers, pp. 46-48, 2012; and Hoeju Chung, et al., “A 58 nm 1.8V 1 Gb PRAM with 6.4 MB/s Program BW”, in ISSCC Dig. Tech. Papers, pp. 500-502, 2011), which is not sufficient for M-type SCM.
As discussed above, DRAM has typically been implemented in such situations (e.g., for M-type SCM applications). However, DRAM is a volatile memory technology. It is therefore desirable to provide a memory architecture for PCM and other non-volatile memory technologies that can support higher (e.g., double-data-rate) speeds.